Emona datex руководство том 2

….. Expt 4 — 1

5 — Amplitude modulation (AM)………………………………………………………………….. (AM)………………………………………………………………….. Expt 5 — 1 6 — Double Sideband (DSBSC) modulation………………………………………………… modulat ion………………………………………………… Expt 6 — 1 7 — Observations of AM and DSBSC DSBSC signals in the frequency frequency domain domain ….. Expt 7 — 1 8 — AM demodulation …………………………………………………………. …………………………………………………………………………………… ……………………….. Expt 8 — 1 9 — Double Sideband DSBSC demodulation….. demodulation ………. ………. ……….. ………… ……….. ……….. ………… ………… ……….. ….. Expt 9 — 1 10 — Single Sideband (SSB) modulation & demodulation demodulation…… ……….. ………. ………. ………. ………. ….. Expt 10 — 1 11 — Frequency Frequency Modulation (FM) ……….. …………….. ………… ………… ………… ………… ……….. ……….. ………… ………… ………… ……….. ….. Expt 11 — 1 12 — FM demodulation…………………………………………. demodulat ion………………………………………………………………………… ………………………………………. ……….. Expt 12 — 1 13 — Sampling & reconstruction ………… ……………… ………… ………… ………… ………… ……….. ……….. ………… ………… ………… ……….. ….. Expt 13 — 1 14 — PCM encoding ………………………………………………………… ……………………………………………………………………………………….. …………………………….. Expt 14 — 1 15 — PCM decoding ………………………………………………………… ……………………………………………………………………………………….. …………………………….. Expt 15 — 1 16 — Bandwidth limiting and restoring digital signals……….. signals……………. ………. ………. ……….. ……….. ….. Expt 16 — 1 17 — Amplitude Shift Keying (ASK) ………. ……………. ………… ……….. ………. ………. ………. ………. ………. ……….. ………… ……….. ….. Expt 17 — 1 18 — Frequency Shift Keying (FSK)………………………… (FSK) ……………………………………………………….. …………………………………. ….. Expt 18 — 1 19 — Binary Phase Shift Keying (BPSK)……………………………………………………… Expt 19 — 1 20 — Quadrature Phase Shift Keying (QPSK) ………. ……………. ………… ……….. ……….. ………… ………… ……….. ….. Expt 20 — 1 21 — Spread Spectrum — DSSS modulation & demodulation demodulation ………. …………… ………. ……… …. Expt 21 — 1 22 — Undersampling Undersampling in Software Defined Radio…………… Radio……………….. ………. ………. ………. ……….. ……….. ….. Expt 22 — 1

  s   n   o    i    t   a   u   q   e    l   e    d   o   m   o    t   x    E    T    A    D   a   n   o   m    E   e    h    t   g   n    i   s    U      4

  :   e   m   a    N

  :   s   s   a    l    C

Experiment 4 – Using the Emona DATEx to model equations Preliminary discussion This may surprise you, but mathematics is an important part of electronics and this is especially true for communications and telecommunications. As you’ll learn, the output of all communications systems can be described mathematically with an equation. Although the math that you’ll need for this manual is relatively light, there is some. Helpfully, the Emona DATEx can model communications equations to bring them to life.

The experiment This experiment will introduce you to modelling equations by using the Emona DATEx to implement two relatively simple equations. It should take you about 40 minutes to complete this experiment.

Equipment 

Personal computer with appropriate software installed



NI ELVIS II plus USB cable and power pack



Emona DATEx experimental add-in module



Two BNC to 2mm banana-plug leads



Assorted 2mm banana-plug patch leads

4-2

© Emona Instruments

Experiment 4 – Using the DATEx to model equations

Something you need to know for the experiment This box contains the definition for an electrical term used in this experiment. Although you’ve probably seen it before, it’s worth taking a minute to read it to check  your understanding. When two signals are 180° out of phase, they’re out of step by half a cycle. This is shown in Figure 1 below. As you can see, the two signals are always travelling in opposite directions. That is, as one goes up, the other goes down (and vice versa).

Figure 1

Experiment 4 – Using the DATEx to model equations

© Emona Instruments

4-3

Procedure In this part of the experiment, you’re going to use the Adder module to add two electrical signals together. Mathematically, you’ll be implementing the equation:

Adder module output = Signal A + Signal B

1.

Ensure that the NI ELVIS II power switch at the back of the unit is off.

2.

Carefully plug the Emona DATEx experimental add-in module into the NI ELVIS II.

3.

Set the Control Mode  switch on the DATEx module (top right corner) to PC Control .

4.

Connect the NI ELVIS II to the PC using the USB cable. Note: This may already have been done for you.

5.

Turn on the NI ELVIS II power switch at the rear of the unit then turn on its Prototyping Board Power  switch at the top right corner near the power indicator.

6.

Turn on the PC and let it boot-up.

7.

Launch the NI ELVISmx software.

Ask the instructor to check  your work before continuing.

8.

Launch and run the NI ELVIS II Oscilloscope virtual instrument (VI).

9.

Set up the scope per the procedure in Experiment 1 (page 1-12) ensuring that the Trigger Source  control is set to CH 0 .

10.

Launch the DATEx soft front-panel (SFP).

11.

Check you now have soft control over the DATEx by activating the PCM Encoder module’s soft PDM/TDM  control on the DATEx SFP. Note: If you’re set-up is working correctly, the PCM Decoder module’s LED on the DATEx board should turn on and off.

4-4

© Emona Instruments

Experiment 4 – Using the DATEx to model equations

12.

Locate the Adder module on the DATEx SFP and set its soft G  and g  controls to about the middle of their travel.

13.

Connect the set-up shown in Figure 2 below. Note: Although not shown, insert the black plugs of the oscilloscope leads into a ground (GND ) socket.

SCOPE 10VDC 7Vrms ma x

MASTER SIGNALS

CH 0

ADDER

CH 1

100kHz SINE G

100kHz COS A

100kHz DIGITAL 8kHz DIGITAL 2kHz DIGITAL

g

2kHz SINE B

GA+gB

Figure 2

This set-up can be represented by the block diagram in Figure 3 below.

A er module

Master Signals A

Output To CH 1

2kHz B

To CH 0 Figure 3

Experiment 4 – Using the DATEx to model equations

© Emona Instruments

4-5

14.

Adjust the scope’s Timebase  control to view two or so cycles of the Master Signals module’s 2kHz SINE  output.

15.

Measure the amplitude (peak-to-peak) of the Master Signals module’s 2kHz SINE  output. Record your measurement in Table 1 on the next page.

16.

Disconnect the lead to the Adder module’s B  input.

17.

Activate the scope’s Channel 1 input by checking the Channel 1 Enabled  box to observe the Adder module’s output as well as its input.

18.

Adjust the Adder module’s soft G  control until its output voltage is the same size as its input voltage (measured in Step 15). Note 1: This makes the gain for the Adder module’s A  input -1. Note 2: Remember that you can use the keyboard’s TAB  and arrow keys for fine adjustment of the DATEx SFP’s controls.

19.

Reconnect the lead to the Adder module’s B  input.

20.

Disconnect the lead to the Adder module’s A  input.

21.

Adjust the Adder module’s soft g  control until its output voltage is the same size as its input voltage (measured in Step 15). Note: This makes the gain for the Adder module’s B  input -1 and means that the Adder module’s two inputs should have the same gain.

22.

Reconnect the lead to the Adder module’s A  input.

The set-up shown in Figures 3 and 4 is now ready to implement the equation:

Adder module output = Signal A + Signal B

Notice though that the Adder module’s two inputs are the same signal: a 4Vp-p 2kHz sinewave. So, for these inputs the equation becomes:

Adder module output = 4Vp-p (2kHz sine) + 4Vp-p (2kHz sine)

4-6

© Emona Instruments

Experiment 4 – Using the DATEx to model equations

When the equation is solved, we get:

Adder module output = 8Vp-p (2kHz sine)

Let’s see if this is what happens in practice.

23.

Measure and record the amplitude of the Adder module’s output.

Table 1

Input voltage

Output voltage

Question 1 Is the Adder module’s measured output voltage exactly 8Vp-p as theoretically predicted? No.

Question 2 What are two reasons for this? 1) Loading (that is, the Adder’s input is not exactly 4Vp-p) 2) The gains aren’t exactly -1.

Ask the instructor to check  your work before continuing.

Experiment 4 – Using the DATEx to model equations

© Emona Instruments

4-7

In the next part of the experiment, you’re going to add two electrical signals together but one of them will be phase shifted. Mathematically, you’ll be implementing the equation:

Adder module output = Signal A + Signal B (with phase shift)

24.

Locate the Phase Shifter module on the DATEx SFP and set its soft Phase Change  control to the 0°  position.

25.

Set the Phase Shifter module’s soft Phase Adjust  control about the middle of its travel.

26.

Connect the set-up shown in Figure 4 below. Note: Insert the black plugs of the oscilloscope leads into a ground (GND ) socket.

SCOPE 10VDC 7Vrms ma x

CH 0

MASTER SIGNALS

PHASE SHIFTER

CH 1

ADDER

LO

100kHz SINE

PHASE

100kHz COS

0

G

O

A

100kHz DIGITAL 180

8kHz DIGITAL

O

2kHz DIGITAL IN

2kHz SINE

OUT

g B

GA+gB

Figure 4

This set-up can be represented by the block diagram in Figure 5 on the next page.

4-8

© Emona Instruments

Experiment 4 – Using the DATEx to model equations

To CH 1

Phase Shifter 2kHz

O

B Output A To CH 0 Figure 5

The set-up shown in Figures 4 and 5 is now ready to implement the equation:

Adder module output = Signal A + Signal B (with phase shift)

The Adder module’s two inputs are still the same signal: a 4Vp-p 2kHz sinewave. So, with values the equation is:

Adder module output = 4Vp-p (2kHz sine) + 4Vp-p (2kHz sine with phase shift)

As the two signals have the same amplitude and frequency, if the phase shift is exactly 180° then their voltages at any point in the waveform is always exactly opposite. That is, when one sinewave is +1V, the other is -1V. When one is +3.75V, the other is -3.75V and so on. This means that, when the equation above is solved, we get:

Adder module output = 0Vp-p

Let’s see if this is what happens in practice.

Experiment 4 – Using the DATEx to model equations

© Emona Instruments

4-9

27.

Adjust the Phase Shifter module’s soft Phase Adjust  control until its input and output signals look like they’re about 180° out of phase with each other.

28.

Disconnect the scope’s Channel 1 lead from the Phase Shifter module’s output and connect it to the Adder module’s output.

29.

Adjust Channel 1’s Scale  control to resize the signal on the display.

30.

Measure the amplitude of the Adder module’s output. Record your measurement in Table 2 below.

Table 2

Output voltage

Question 3 What are two reasons for the output not being 0V as theoretically predicted? 1) The phase difference between the Adder’s two inputs is not exactly 180°; and 2) The gains aren’t exactly the same.

Ask the instructor to check  your work before continuing.

4-10

© Emona Instruments

Experiment 4 – Using the DATEx to model equations

The following procedure can be used to adjust the Adder and Phase Shifter modules so that the set-up has a null  output. That is, an output that is close to zero volts.

31.

Use the keyboard’s TAB  and arrow keys to vary the Phase Shifter module’s soft Phase Adjust  control left and right a little and observe the effect on the Adder module’s output.

32.

Use the keyboard to make the necessary fine adjustments to the Phase Shifter module’s soft Phase Adjust  control to obtain the smallest output voltage from the Adder module.

Question 5 What can be said about the phase shift between the signals on the Adder module’s two inputs now? The phase shift is much closer to 180° (but it’s probably still not exactly 180°)

33.

Use the keyboard to vary the Adder module’s soft g  control left and right a little and observe the effect on the Adder module’s output.

34.

Use the keyboard to make the necessary fine adjustments to the Adder module’s soft g  control to obtain the smallest output voltage.

Question 6 What can be said about the gain of the Adder module’s two inputs now? They’re much closer to each other (but they’re still probably not exactly the same)

You’ll probably find that you’ll not be able to null the Adder module’s output completely. Unfortunately, real systems are never perfect and so they don’t behave exactly according to theory. As such, it’s important for you to learn to recognise these limitations, understand their origins and quantify them where necessary.

Ask the instructor to check  your work before finishing.

Experiment 4 – Using the DATEx to model equations

© Emona Instruments

4-11

4-12

© Emona Instruments

Experiment 4 – Using the DATEx to model equations

Emona DATEx VOLUME 2 Contents 

Introduction ………………………………………………………………………………………….. i — iv 1 — AM (method 2) and product detection of AM signals……………………….. Expt 1 — 1 2 — Noise in AM communications………………………………………………………………… Expt 2 — 1 3 — PCM and time division multiplexing (TDM) …………………………………………. Expt 3 — 1 4 — An introduction to Armstrong’s modulator ………………………………………… Expt 4 — 1 5 — Phase division modulation and demodulation ………………………………………. Expt 5 — 1 6 — Pulse-width modulation and demodulation………………………………………….. Expt 6 — 1 7 — Message translation and inversion ………………………………………………………. Expt 7 — 1 8 — Carrier acquisition using the phase-locked loop ………………………………… Expt 8 — 1 9 — Signal-to-noise ratio and eye diagrams………………………………………………. Expt 9 — 1 10 — Pulse code modulation and signal-to-noise distortion ratio (SNDR) Expt 10 — 1 11 — ASK demodulation using product detection………………………………………. Expt 11 — 1 12 — FSK generation (switching method) and demodulation……………………. Expt 12 — 1 13 — Principles of Gaussian FSK (GFSK) ……………………………………………………. Expt 13 — 1 14 — PN sequence spectra and noise generation

….Expt 14 — 1 15 — Line coding and bit-clock regeneration …………………………………………….. Expt 15 – 1 16 — Delta modulation and demodulation …………………………………………………… Expt 16 — 1 17 – Delta-sigma modulation and demodulation………………………………………… Expt 17 – 1 18 – FM Generation using the harmonic multiplier method…………………….. Expt 18 — 1

  n   o    i    t   a   r   e   n   e   g   e   s    i   o   n    d   n   a   a   r    t   c   e   p   s   e   c   n   e   u   q   e   s    N    P      4    1   :   e   m   a    N

  :   s   s   a    l    C

Experiment 14 – PN sequence spectra and noise generation Preliminary discussion Pseudo-noise sequences (or just PN sequences) are very useful signals in communications and telecommunications, especially for implementing modulation schemes such as DSSS and CDMA (among others). They can also be used to generate noise for experimental purposes when modelling real world communications systems. But what exactly is a PN sequence?

To understand the answer to this question, you must return to the spectral composition of pulse trains. Recall that a pulse train is made up of a theoretically infinite number of sinewaves – the fundamental and its harmonics. Recall also that the frequency and amplitude of a pulse train’s sinusoidal components affects its frequency and mark-space ratio (or duty cycle). Despite this, the spectral composition of all pulse trains follows the pattern of the (truncated) Sinc Function  shown in Figure 1 below. 1 0.8 0.6 0.4 0.2 0 1

2

3

4

-0.2 -0.4

Figure 1

Figure 2 below illustrates this with an example of a 1kHz squarewave (a pulse train with a mark-space ratio of 1:1 or a duty cycle 50%). This is a spectrum that would be familiar to you.

500µs

1 0.8

1kHz (1:1)

0.6

1ms

0.4 0.2 0

3kHz

7kHz and so on…

1kHz

5kHz

-0.2 -0.4

Figure 2

14-2

© Emona Instruments

Experiment 14 – PN sequence spectra & noise generation

Figure 3 below shows the spectral composition of a 1kHz pulse train pulse having a mark-space ratio of 1:3 (or a duty cycle 25%). Notice that it too follows the pattern of the Sinc Function. 250µs 1 0.8

1kHz (1:3)

0.6

1ms

0.4 0.2 0

5kHz 6k 7 kHz 1kHz 2k 3kHz

9kHz and so on…

-0.2 -0.4

Figure 3

The examples in Figures 2 and 3 are instructive. Together, they show us that some harmonics of the pulse trains have an amplitude of zero (or are “nulled”) and this is true of all pulse trains. Second, a comparison of Figures 2 and 3 shows us that, as the pulse train’s mark-space ratio decreases, the number of significant harmonics that make it up increases. Or, put another way, as the mark-space ratio decreases, the number of harmonics that are present in each of the Sinc Function’s lobes increases. Now, suppose a sequence generator continuously outputs the sequential 4-bit binary number 1000 with each bit being 250µs wide (requiring a bit-clock of 4kHz). In the time domain, the resulting digital data signal is identical to the pulse train in Figure 3. This means that the sequence’s spectral composition must be identical to the spectrum in Figure 3 also. This fact has a couple of important implications. First, we can establish a general rule for determining the nulled harmonics in repeated sequential binary number sequences. They correspond with whole number multiples of the digital signal’s bit-clock (that is, fbit, 2fbit, 3fbit and so on). In the case of our repeated sequential 4-bit binary number 1000 generated using a 4kHz bit-clock, the nulls occur at 4kHz, 8kHz, 12kHz and so on to infinity (theoretically). Second, if the sequence generator’s continuously repeated output is changed to the 5-bit binary number sequence 10000, the mark-space ratio of the resulting digital data signal decreases and so more harmonics are present between the nulls. Importantly though, if a 4kHz bit-clock is used to generate the 5-bit sequence, the nulls occur at the same frequencies as our example in Figure 3. So, with the nulls occurring at the same frequencies but with more harmonics between them, the spectral composition of the 5-bit sequence must be richer than that of its 4-bit counterpart. This gives us a second general rule. The greater the number of bits in a repeated sequence for a given bit-clock, the greater the sequence’s spectral composition (though this doesn’t apply to PN sequences with internally repeated sequences like 101010… and 11001100…).

Experiment 14 – PN sequence spectra & noise generation

© Emona Instruments

14-3

Using the Sinc Function to analyse the spectral composition of several binary number sequences like 1000, 10000, 100000 and so on would quickly show that the number of harmonics in each lobe is the same number as the sequence’s length (though the last one is nulled). Finally, we can now return to the question of what is a pseudo-noise sequence. If the length of certain binary number sequences is long enough, their spectral composition becomes so dense that it can be used to model bandwidth limited white noise. That said, there would still be a repetitive element to the “noise signal” and so they’re called pseudo (or “apparent”) noise sequences.

The experiment For this experiment you’ll use the Emona DATEx to consider a 31-bit and 255-bit binary number sequence in the time domain. You’ll then look at the data signals’ spectra in the frequency domain to confirm their spectral composition. Finally, you’ll use the sequences to generate electrical noise and compare their effectiveness.

It should take you about 50 minutes to complete this experiment.

Pre-requisites: Experiments 1, 2 & 3 (Vol. 1): Intros to the NI ELVIS II, the Emona DATEx and SFP control

Equipment 

Personal computer with appropriate software installed



NI ELVIS II plus USB cable and power pack



Emona DATEx experimental add-in module



Three BNC to 2mm banana-plug leads



Assorted 2mm banana-plug patch leads

14-4

© Emona Instruments

Experiment 14 – PN sequence spectra & noise generation

Procedure Part A – Observations of PN sequences in the time domain The next part of this experiment gets you to set up a 31-bit and a 255-bit binary number sequence and consider them in the time domain as preparation for looking at their spectra.

1.

Ensure that the NI ELVIS II power switch at the back of the unit is off.

2.

Carefully plug the Emona DATEx experimental add-in module into the NI ELVIS II.

3.

Set the Control Mode  switch on the DATEx module (top right corner) to PC Control .

4.

Connect the NI ELVIS II to the PC using the USB cable. Note: This may already have been done for you.

5.

Turn on the NI ELVIS II power switch at the rear of the unit then turn on its Prototyping Board Power  switch at the top right corner near the power indicator.

6.

Turn on the PC and let it boot-up.

7.

Launch the NI ELVISmx software.

8.

Connect the set-up shown in Figure 4 below. Note: Insert the black plugs of the oscilloscope leads into a ground (GND ) socket.

MASTER SIGNALS

SEQUENCE GENERATOR LINE CODE O

FGEN TRIG 5V TTL

1 OONRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M 100kHz SINE

CH 0

X

100kHz COS

SCOPE 10VDC 7Vrms ma x

Y CLK

100kHz DIGITAL

SPEECH

CH 1

8kHz DIGITAL 2kHz DIGITAL GND 2kHz SINE GND

Figure 4

Experiment 14 – PN sequence spectra & noise generation

© Emona Instruments

14-5

1 Emona DATEx Lab Manual Volume 2 Further Experiments in Modern Analog & Digital Telecommunications For NI ELVIS I and II Barry Duncan

2 .

3 Emona DATEx Lab Manual Volume 2 Further Experiments in Modern Analog & Digital Telecommunications For NI ELVIS I and II Barry Duncan

4 Emona DATEx Lab Manual for NI ELVIS I and II Volume 2 — Further Experiments in Modern Analog and Digital Telecommunications. Author: Barry Duncan Technical editor: Carlo Manfredini Issue Number: Vol2 issue 1.1 Published by: Emona Instruments Pty Ltd, 78 Parramatta Road Camperdown NSW 2050 AUSTRALIA. web: telephone: fax: Copyright Emona Instruments Pty Ltd and its related entities. All rights reserved. No part of this publication may be reproduced, translated, adapted, modified, edited or distributed in any form or by any means, including any network or Web distribution or broadcast for distance learning, or stored in any database or in any network retrieval system, without the prior written consent of Emona Instruments Pty Ltd. For licensing information, please contact Emona Instruments Pty Ltd. DATEx is a trademark of Emona TIMS Pty Ltd. LabVIEW, National Instruments, NI, NI ELVIS, and NI-DAQ are trademarks of National Instruments Corporation. Product and company names mentioned herein are trademarks or trade names of their respective companies. Printed in Australia

5 Contents Introduction… i — iv 1 — AM (method 2) and product detection of AM signals… Expt Noise in AM communications… Expt PCM and time division multiplexing (TDM)… Expt An introduction to Armstrong s modulator… Expt Phase division modulation and demodulation… Expt Pulse-width modulation and demodulation… Expt Message translation and inversion… Expt Carrier acquisition using the phase-locked loop… Expt Signal-to-noise ratio and eye diagrams… Expt Pulse code modulation and signal-to-noise distortion ratio (SNDR) Expt ASK demodulation using product detection… Expt FSK generation (switching method) and demodulation… Expt Principles of Gaussian FSK (GFSK)… Expt PN sequence spectra and noise generation… Expt Line coding and bit-clock regeneration… Expt Delta modulation and demodulation… Expt Delta-sigma modulation and demodulation… Expt FM Generation using the harmonic multiplier method… Expt 18-1

6

7 i

8

9 iii

10

11

12

13

14

15 MASTER SIGNALS SINE COS 8kHz SINE MULTIPLIER DC Y AC kxy MULTIPLIER X DC Y DC DC X AC kxy SCOPE 10VDC 7Vrms max CH 0 CH 1

16

17 Y DC AC MULTIPLIER MULTIPLIER kxy X DC Y DC kxy DC X AC MASTER SIGNALS SINE COS 8kHz SINE CH 0 CH 1 SCOPE 10VDC 7Vrms max B A ADDER G GA+gB g IN OUT 0 O 180 O PHASE PHASE SHIFTER LO

18

19

20 V LSB USB LSB Carrier USB f Carrier

21

22

23 MASTER SIGNALS MULTIPLIER DC X AC PHASE SHIFTER LO ADDER SCOPE 10VDC 7Vrms max CH 0 SINE COS 8kHz SINE DC Y AC kxy MULTIPLIER X DC Y DC kxy PHASE 0 O 180 O IN OUT A B G g GA+gB CH 1

24

25 MASTER SIGNALS MULTIPLIER DC X AC PHASE SHIFTER LO ADDER UTILITIES COMPARATOR REF SCOPE 10VDC 7Vrms max CH 0 SINE COS 8kHz SINE DC Y AC kxy MULTIPLIER X DC Y DC kxy PHASE 0 O 180 O IN OUT A B G g GA+gB IN OUT RECTIFIER DIODE & RC LPF RC LPF CH 1

26

27

28

29

30 = = = + =

31

32

33 MASTER SIGNALS FUNCTION GENERATOR ADDER MULTIPLIER SINE COS 8kHz SINE ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + A B G g GA+gB DC Y AC kxy MULTIPLIER X DC Y DC DC X AC kxy SCOPE 10VDC 7Vrms max CH 0 CH 1

34

35 MASTER SIGNALS FUNCTION GENERATOR ADDER MULTIPLIER SINE COS 8kHz SINE ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + A B G g GA+gB DC Y AC kxy MULTIPLIER X DC Y DC DC X AC kxy SCOPE 10VDC 7Vrms max CH 0 CH 1 NOISE GENERATOR 0dB -6dB -20dB AMPLIFIER CHANNEL MODULE CHANNEL BPF BASEBAND LPF ADDER UTILITIES COMPARATOR REF IN OUT RECTIFIER GAIN NOISE DIODE & RC LPF IN OUT SIGNAL CHANNEL OUT RC LPF

36

37 MASTER SIGNALS FUNCTION GENERATOR ADDER MULTIPLIER SINE COS 8kHz SINE ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + A B G g GA+gB DC Y AC kxy MULTIPLIER X DC Y DC DC X AC kxy SCOPE 10VDC 7Vrms max CH 0 CH 1 NOISE GENERATOR 0dB -6dB -20dB AMPLIFIER CHANNEL MODULE CHANNEL BPF BASEBAND LPF ADDER UTILITIES COMPARATOR REF IN OUT RECTIFIER GAIN NOISE DIODE & RC LPF IN OUT SIGNAL CHANNEL OUT RC LPF

38

39 + =

40

41 MASTER SIGNALS FUNCTION GENERATOR ADDER MULTIPLIER SINE COS 8kHz SINE ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + A B G g GA+gB DC Y AC kxy MULTIPLIER X DC Y DC DC X AC kxy SCOPE 10VDC 7Vrms max CH 0 CH 1

42 MASTER SIGNALS FUNCTION GENERATOR ADDER MULTIPLIER SINE COS 8kHz SINE ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + A B G g GA+gB DC Y AC kxy MULTIPLIER X DC Y DC DC X AC kxy SCOPE 10VDC 7Vrms max CH 0 CH 1 NOISE GENERATOR CHANNEL MODULE MULTIPLIER UTILITIES COMPARATOR REF 0dB -6dB CHANNEL BPF X DC -20dB AMPLIFIER GAIN NOISE BASEBAND LPF ADDER Y DC kxy SERIAL TO PARALLEL S/ P IN OUT RECTIFIER DIODE & RC LPF IN OUT SIGNAL CHANNEL OUT SERIAL X1 RC LPF CLK X2

43

44 MASTER SIGNALS FUNCTION GENERATOR ADDER MULTIPLIER SINE COS 8kHz SINE ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + A B G g GA+gB DC Y AC kxy MULTIPLIER X DC Y DC DC X AC kxy SCOPE 10VDC 7Vrms max CH 0 CH 1 NOISE GENERATOR CHANNEL MODULE MULTIPLIER UTILITIES COMPARATOR REF 0dB -6dB CHANNEL BPF X DC -20dB AMPLIFIER GAIN NOISE BASEBAND LPF ADDER Y DC kxy SERIAL TO PARALLEL S/ P IN OUT RECTIFIER DIODE & RC LPF IN OUT SIGNAL CHANNEL OUT SERIAL X1 RC LPF CLK X2

45

46 + =

47

48

49

50

51

52

53 FUNCTION GENERATOR MASTER SIGNALS PCM ENCODER PCM DECODER TUNEABLE LPF GND ANALOG I/ O ACH1 DAC1 SINE COS PCM TDM INPUT 2 FS FS TDM f C x100 f C SCOPE 10VDC 7Vrms max CH 0 ACH0 DAC0 VARIABLE DC + 8kHz SINE INPUT 1 CLK PCM DATA PCM DATA CLK OUTPUT2 OUTPUT GAIN CH 1 IN OUT

54

55

56

57

58

59 FUNCTION GENERATOR MASTER SIGNALS PCM ENCODER PCM DECODER TUNEABLE LPF GND ANALOG I/ O ACH1 DAC1 SINE COS PCM TDM INPUT 2 FS FS TDM f C x100 f C SCOPE 10VDC 7Vrms max CH 0 ACH0 DAC0 VARIABLE DC + 8kHz SINE INPUT 1 CLK PCM DATA PCM DATA CLK OUTPUT2 OUTPUT GAIN CH 1 IN OUT

60 PCM ENCODER FS CLK PCM DATA TDM INPUT 2 INPUT 1 PCM MASTER SIGNALS SINE COS 8kHz SINE PCM DECODER FS PCM DATA CLK OUTPUT TDM OUTPUT2 GND f C x100 f C GAIN IN OUT TUNEABLE LPF VARIABLE DC FUNCTION GENERATOR + ANALOG I/ O ACH1 DAC1 ACH0 DAC0 AMPLIFIER GAIN OUT IN 0dB -6dB -20dB NOISE GENERATOR

61 MASTER SIGNALS PCM ENCODER PCM DECODER TUNEABLE LPF NOISE GENERATOR GND 0dB PCM TDM TDM f C x100-6db -20dB SINE COS 8kHz SINE INPUT 2 INPUT 1 CLK FS PCM DATA FS PCM DATA CLK OUTPUT2 OUTPUT f C GAIN IN OUT AMPLIFIER GAIN IN OUT SEQUENCE GENERATOR O 1 OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M X LINE CODE CHANNEL MODULE CHANNEL BPF BASEBAND LPF CLK Y SPEECH NOISE ADDER GND GND SIGNAL CHANNEL OUT

62

63

64

65 θ θ

66 θ θ

67 MASTER SIGNALS SINE COS 8kHz SINE MULTIPLIER DC Y AC kxy MULTIPLIER X DC Y DC DC X AC kxy SCOPE 10VDC 7Vrms max CH 0 CH 1

68

69 MASTER SIGNALS MULTIPLIER DC X AC PHASE SHIFTER LO ADDER SCOPE 10VDC 7Vrms max CH 0 SINE COS 8kHz SINE DC Y AC kxy MULTIPLIER X DC Y DC kxy PHASE 0 O 180 O IN OUT A B G g GA+gB CH 1

70

71

72

73 MASTER SIGNALS MULTIPLIER PHASE SHIFTER ADDER UTILITIES COMPARATOR REF NOISE GENERATOR DC X AC LO 0dB -6dB SINE COS 8kHz SINE DC Y AC kxy MULTIPLIER X DC Y DC kxy PHASE 0 O 180 O IN OUT A B G g GA+gB IN OUT RECTIFIER DIODE & RC LPF RC LPF -20dB AMPLIFIER GAIN IN OUT

74 MASTER SIGNALS MULTIPLIER DC X AC PHASE SHIFTER LO ADDER SCOPE 10VDC 7Vrms max CH 0 SINE COS 8kHz SINE DC Y AC kxy MULTIPLIER X DC Y DC kxy PHASE 0 O 180 O IN OUT A B G g GA+gB CH 1 UTILITIES COMPARATOR REF CHANNEL MODULE CHANNEL BPF GND IN OUT RECTIFIER DIODE & RC LPF NOISE BASEBAND LPF ADDER RC LPF SIGNAL CHANNEL OUT

75

76

77

78 Π

79 Π

80

81 FUNCTION GENERATOR MASTER SIGNALS MULTIPLIER ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + SINE COS 8kHz SINE DC Y AC kxy MULTIPLIER X DC Y DC DC X AC kxy SCOPE 10VDC 7Vrms max CH 0 CH 1

82

83 FUNCTION GENERATOR MASTER SIGNALS MULTIPLIER ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + SINE COS 8kHz SINE DC Y AC kxy MULTIPLIER X DC Y DC DC X AC kxy SCOPE 10VDC 7Vrms max CH 0 CH 1

84 FUNCTION GENERATOR MASTER SIGNALS MULTIPLIER ADDER ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + SINE COS 8kHz SINE DC Y AC kxy MULTIPLIER X DC Y DC DC X AC kxy A B G g GA+gB SCOPE 10VDC 7Vrms max CH 0 CH 1

85

86

87

88

89 FUNCTION GENERATOR MASTER SIGNALS MULTIPLIER ADDER ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + SINE COS 8kHz SINE DC Y AC kxy MULTIPLIER X DC Y DC DC X AC kxy A B G g GA+gB SCOPE 10VDC 7Vrms max CH 0 CH 1 PHASE SHIFTER MULTIPLIER TUNEABLE LPF LO X DC f C x100 PHASE 0 O 180 O Y DC kxy SERIAL TO PARALLEL S/ P f C IN OUT SERIAL X1 GAIN CLK X2 IN OUT

90 O

91 FUNCTION GENERATOR MASTER SIGNALS MULTIPLIER ADDER ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + SINE COS 8kHz SINE DC Y AC kxy MULTIPLIER X DC Y DC DC X AC kxy A B G g GA+gB SCOPE 10VDC 7Vrms max CH 0 CH 1 PHASE SHIFTER MULTIPLIER TUNEABLE LPF LO X DC f C x100 PHASE 0 O 180 O Y DC kxy SERIAL TO PARALLEL S/ P f C IN OUT SERIAL X1 GAIN CLK X2 IN OUT

92 FUNCTION GENERATOR MASTER SIGNALS MULTIPLIER ADDER ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + SINE COS 8kHz SINE DC Y AC kxy MULTIPLIER X DC Y DC DC X AC kxy A B G g GA+gB SCOPE 10VDC 7Vrms max CH 0 CH 1 PHASE SHIFTER MULTIPLIER TUNEABLE LPF NOISE GENERATOR 0dB LO X DC f C x100-6db -20dB PHASE 0 O Y DC kxy SERIAL TO PARALLEL S/ P f C AMPLIFIER 180 O GAIN IN OUT SERIAL X1 GAIN IN OUT CLK X2 IN OUT

93

94

95

96

97 V Sawtooth input V Sawtooth input Analog input Analog input t t Vout Vout t t Va Vout t t

98

99 MASTER SIGNALS TWIN PULSE GENERATOR UTILITIES COMPARATOR REF SINE COS 8kHz SINE WIDTH Q2 DELAY CLK Q1 IN OUT RECTIFIER DIODE & RC LPF RC LPF SCOPE 10VDC 7Vrms max CH 0 CH 1

100

101 FUNCTION GENERATOR MASTER SIGNALS TWIN PULSE GENERATOR UTILITIES COMPARATOR REF ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + SINE COS 8kHz SINE WIDTH Q2 DELAY CLK Q1 IN OUT RECTIFIER DIODE & RC LPF RC LPF SCOPE 10VDC 7Vrms max CH 0 CH 1

102 FUNCTION GENERATOR MASTER SIGNALS TWIN PULSE GENERATOR UTILITIES COMPARATOR REF ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + SINE COS 8kHz SINE WIDTH Q2 DELAY CLK Q1 IN OUT RECTIFIER DIODE & RC LPF RC LPF SCOPE 10VDC 7Vrms max CH 0 CH 1

103

104 FUNCTION GENERATOR ADDER MASTER SIGNALS TWIN PULSE GENERATOR UTILITIES COMPARATOR REF ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + A B G g GA+gB SINE COS 8kHz SINE WIDTH Q2 DELAY CLK Q1 IN OUT RECTIFIER DIODE & RC LPF RC LPF SCOPE 10VDC 7Vrms max CH 0 CH 1

105

106 FUNCTION GENERATOR ADDER MASTER SIGNALS TWIN PULSE GENERATOR UTILITIES COMPARATOR REF ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + A B G g GA+gB SINE COS 8kHz SINE WIDTH Q2 DELAY CLK Q1 IN OUT RECTIFIER DIODE & RC LPF RC LPF SCOPE 10VDC 7Vrms max CH 0 CH 1

107

108

109 FUNCTION GENERATOR ADDER MASTER SIGNALS TWIN PULSE GENERATOR UTILITIES COMPARATOR REF TUNEABLE LPF ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + A B G g GA+gB SINE COS 8kHz SINE WIDTH Q2 DELAY CLK Q1 IN OUT RECTIFIER DIODE & RC LPF RC LPF f C x100 f C GAIN IN OUT SCOPE 10VDC 7Vrms max CH 0 CH 1

110

111 FUNCTION GENERATOR ADDER MASTER SIGNALS TWIN PULSE GENERATOR UTILITIES COMPARATOR REF TUNEABLE LPF NOISE GENERATOR 0dB f C x100-6db ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + A B G g GA+gB SINE COS 8kHz SINE WIDTH Q2 DELAY CLK Q1 IN OUT RECTIFIER DIODE & RC LPF RC LPF f C GAIN IN OUT -20dB AMPLIFIER GAIN IN OUT

112

113 FUNCTION GENERATOR ADDER MASTER SIGNALS TWIN PULSE GENERATOR UTILITIES COMPARATOR REF TUNEABLE LPF f C x100 ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + A B G g GA+gB SINE COS 8kHz SINE WIDTH Q2 DELAY CLK Q1 IN OUT RECTIFIER DIODE & RC LPF RC LPF f C GAIN IN OUT SCOPE 10VDC 7Vrms max CH 0 CH 1

114

115

116

117

118 f 300Hz 3000Hz f (khz) 103 f (khz) f (khz) f (khz)

119 f (khz) f (khz)

120

121

122 MASTER SIGNALS MULTIPLIER DC X AC TUNEABLE LPF f C x100 SCOPE 10VDC 7Vrms max CH 0 SINE COS 8kHz SINE DC Y AC MULTIPLIER X DC Y DC kxy kxy IN f C GAIN OUT CH 1 FUNCTION GENERATOR CHANNEL MODULE NOISE GENERATOR CHANNEL BPF 0dB -6dB ANALOG I/ O ACH1 DAC1 BASEBAND LPF ADDER -20dB AMPLIFIER ACH0 DAC0 VARIABLE DC + NOISE SIGNAL CHANNEL OUT IN GAIN OUT

123

124

125

126

127 MASTER SIGNALS MULTIPLIER DC X AC TUNEABLE LPF f C x100 SCOPE 10VDC 7Vrms max CH 0 SINE COS 8kHz SINE DC Y AC MULTIPLIER X DC Y DC kxy kxy IN f C GAIN OUT CH 1 SEQUENCE GENERATOR O 1 OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M CLK X Y LINE CODE SPEECH CHANNEL MODULE NOISE CHANNEL BPF BASEBAND LPF ADDER NOISE GENERATOR 0dB -6dB -20dB AMPLIFIER GAIN GND GND SIGNAL CHANNEL OUT IN OUT

128

129

130

131

132

133

134 MASTER SIGNALS TUNEABLE LPF SINE COS 8kHz SINE IN f C GAIN f C x10 0 OUT SCOPE 10VDC 7Vrms max CH 0 CH 1

135 MASTER SIGNALS TUNEABLE LPF MULTIPLIER SCOPE 10VDC 7Vrms max CH 0 f C x100 X DC CH 1 SINE COS f C Y DC kxy SERIAL TO PARALLEL S/ P 8kHz GAIN SERIAL X1 SINE IN OUT CLK X2

136

137 MASTER SIGNALS TUNEABLE LPF f C x100 MULTIPLIER X DC SCOPE 10VDC 7Vrms max CH 0 CH 1 SINE COS 8kHz f C GAIN Y DC SERIAL kxy SERIAL TO PARALLEL S/ P X1 SINE IN OUT CLK X2 MULTIPLIER UTILITIES COMPARATOR ADDER FUNCTION GENERATOR REF DC X AC DC Y AC kxy MULTIPLIER X DC IN OUT RECTIFIER DIODE & RC LPF RC LPF A G g ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + Y DC kxy B GA+gB

138

139

140

141

142 = = = + =

143

144 NOISE GENERATOR SEQUENCE GENERATOR CHANNEL MODULE FGEN 0dB -6dB -20dB AMPLIFIER O 1 LINE CODE OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M X CHANNEL BPF BASEBAND LPF TRIG 5V TTL SCOPE 10VDC 7Vrms max CH 0 GAIN CLK Y SPEECH NOISE ADDER CH 1 IN OUT GND GND SIGNAL CHANNEL OUT

145

146

147 NOISE GENERATOR SEQUENCE GENERATOR CHANNEL MODULE FGEN 0dB O LINE CODE TRIG 5V TTL -6dB -20dB AMPLIFIER 1 OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M X CHANNEL BPF BASEBAND LPF SCOPE 10VDC 7Vrms max CH 0 GAIN CLK Y SPEECH NOISE ADDER CH 1 IN OUT GND SIGNAL CHANNEL OUT GND

148

149

150

151

152

153

154 NOISE GENERATOR FUNCTION GENERATOR SEQUENCE GENERATOR CHANNEL MODULE FGEN AMPLIFIER IN 0dB -6dB -20dB GAIN OUT ANALOG I/ O ACH1 ACH0 VARIABLE DC + DAC1 DAC0 O 1 OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M CLK SPEECH GND GND X Y LINE CODE NOISE BASEBAND LPF SIGNAL CHANNEL BPF ADDER CHANNEL OUT TRIG 5V TTL SCOPE 10VDC 7Vrms max CH 0 CH 1

155

156

157

158

159

160

161 = + = O

162

163 MASTER SIGNALS PCM ENCODER PCM DECODER GND SINE COS 8kHz SINE PCM TDM INPUT 2 INPUT 1 CLK FS PCM DATA FS PCM DATA CLK TDM OUTPUT2 OUTPUT SCOPE 10VDC 7Vrms max CH 0 CH 1

164

165

166 PCM ENCODER FS CLK PCM DATA TDM INPUT 2 INPUT 1 PCM MASTER SIGNALS SINE COS 8kHz SINE PCM DECODER FS PCM DATA CLK OUTPUT TDM OUTPUT2 GND CH 0 CH 1 SCOPE 10VDC 7Vrms max B A ADDER G GA+gB g IN OUT 0 O 180 O PHASE PHASE SHIFTER LO

167 O O

168

169 + =

170

171 MASTER SIGNALS PCM ENCODER PCM DECODER UTILITIES COMPARATOR REF GND SINE COS PCM TDM INPUT 2 FS FS TDM IN OUT RECTIFIER SCOPE 10VDC 7Vrms max CH 0 8kHz SINE INPUT 1 CLK PCM DATA PCM DATA CLK OUTPUT2 OUTPUT DIODE & RC LPF RC LPF CH 1 PHASE SHIFTER ADDER LO PHASE 0 O 180 O A G IN OUT g B GA+gB

172

173 MASTER SIGNALS PCM ENCODER PCM DECODER UTILITIES COMPARATOR REF GND SINE COS PCM TDM INPUT 2 FS FS TDM IN OUT RECTIFIER SCOPE 10VDC 7Vrms max CH 0 8kHz SINE INPUT 1 CLK PCM DATA PCM DATA CLK OUTPUT2 OUTPUT DIODE & RC LPF RC LPF CH 1 PHASE SHIFTER ADDER LO PHASE 0 O 180 O A G IN OUT g B GA+gB

174 O

175

176 MASTER SIGNALS PCM ENCODER PCM DECODER TUNEABLE LPF GND SINE COS 8kHz SINE PCM TDM INPUT 2 INPUT 1 CLK FS PCM DATA FS PCM DATA CLK TDM OUTPUT2 OUTPUT f C x100 f C GAIN IN OUT SCOPE 10VDC 7Vrms max CH 0 CH 1 PHASE SHIFTER ADDER LO PHASE 0 O 180 O A G IN OUT g B GA+gB

177 MASTER SIGNALS PCM ENCODER PCM DECODER TUNEABLE LPF GND SINE COS 8kHz SINE PCM TDM INPUT 2 INPUT 1 CLK FS PCM DATA FS PCM DATA CLK TDM OUTPUT2 OUTPUT f C x100 f C GAIN IN OUT SCOPE 10VDC 7Vrms max CH 0 CH 1 PHASE SHIFTER ADDER LO PHASE 0 O 180 O A G IN OUT g B GA+gB

178 O

179

180

181

182

183

184

185 MASTER SIGNALS SEQUENCE GENERATOR DUAL ANALOG SWITCH FGEN O LINE CODE S/ H TRIG 5V TTL SINE 1 OO NRZ-L O1 Bi-O SYNC 1O RZ-AMI 11 NRZ-M X S&H IN IN 1 S&H OUT SCOPE 10VDC 7Vrms max CH 0 COS 8kHz CLK Y SPEECH CONTROL 1 CONTROL 2 CH 1 SINE GND GND IN 2 OUT

186

187 MASTER SIGNALS SEQUENCE GENERATOR DUAL ANALOG SWITCH MULTIPLIER TUNEABLE LPF FGEN SINE COS 8kHz CLK O 1 OO NRZ-L O1 Bi-O 1O RZ-AMI 11 NRZ-M X Y LINE CODE SYNC SPEECH S&H IN IN 1 S/ H CONTROL 1 CONTROL 2 S&H OUT X DC Y DC kxy SERIAL TO PARALLEL S/ P f C x100 f C TRIG 5V TTL SCOPE 10VDC 7Vrms max CH 0 CH 1 SINE GND GND IN 2 OUT SERIAL CLK X1 X2 GAIN IN OUT

188

189

190 MASTER SIGNALS SEQUENCE GENERATOR DUAL ANALOG SWITCH MULTIPLIER TUNEABLE LPF FGEN SINE COS 8kHz O 1 OO NRZ-L O1 Bi-O 1O RZ-AMI 11 NRZ-M CLK X Y LINE CODE SYNC SPEECH S&H IN IN 1 S/ H CONTROL 1 CONTROL 2 S&H OUT X DC Y DC kxy SERIAL TO PARALLEL S/ P f C f C x100 TRIG 5V TTL SCOPE 10VDC 7Vrms max CH 0 CH 1 SINE GND GND IN 2 OUT SERIAL CLK X1 X2 IN GAIN OUT PHASE SHIFTER LO PHASE 0 O 180 O IN OUT

191

192

193

194 MASTER SIGNALS SEQUENCE GENERATOR DUAL ANALOG SWITCH MULTIPLIER TUNEABLE LPF FGEN SINE COS 8kHz O 1 OO NRZ-L O1 Bi-O 1O RZ-AMI 11 NRZ-M CLK X Y LINE CODE SYNC SPEECH S&H IN IN 1 S/ H CONTROL 1 CONTROL 2 S&H OUT X DC Y DC kxy SERIAL TO PARALLEL S/ P f C f C x100 TRIG 5V TTL SCOPE 10VDC 7Vrms max CH 0 CH 1 SINE GND GND IN 2 OUT SERIAL CLK X1 X2 IN GAIN OUT FUNCTION GENERATOR ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC +

195

196

197

198

199

200

201 MASTER SIGNALS SEQUENCE GENERATOR O LINE CODE FUNCTION GENERATOR UTILITIES COMPARATOR REF FGEN TRIG 5V TTL 1 SINE COS 8kHz SINE OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M CLK SPEECH GND GND X Y ANALOG I/ O ACH1 ACH0 VARIABLE DC + DAC1 DAC0 IN OUT RECTIFIER DIODE & RC LPF RC LPF SCOPE 10VDC 7Vrms max CH 0 CH 1

202

203 MASTER SIGNALS SINE COS 8kHz SINE SEQUENCE GENERATOR O 1 OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M CLK SPEECH GND GND X Y LINE CODE FUNCTION GENERATOR ANALOG I/ O ACH1 ACH0 DAC0 VARIABLE DC + DAC1 UTILITIES COMPARATOR REF IN RECTIFIER DIODE & RC LPF RC LPF OUT FGEN TRIG 5V TTL SCOPE 10VDC 7Vrms max CH 0 CH 1 DUAL ANALOG SWITCH S/ H S&H IN S&H OUT IN 1 CONTROL 1 CONTROL 2 IN 2 OUT

204

205

206

207

208

209 MASTER SIGNALS SEQUENCE GENERATOR O LINE CODE FUNCTION GENERATOR UTILITIES COMPARATOR REF FGEN TRIG 5V TTL 1 SINE COS 8kHz SINE OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M CLK SPEECH GND GND X Y ANALOG I/ O ACH1 ACH0 DAC0 VARIABLE DC + DAC1 IN OUT RECTIFIER DIODE & RC LPF RC LPF SCOPE 10VDC 7Vrms max CH 0 CH 1 DUAL ANALOG SWITCH TUNEABLE LPF S/ H S&H IN S&H OUT f C x100 IN 1 CONTROL 1 CONTROL 2 f C GAIN IN 2 OUT IN OUT

210

211 MASTER SIGNALS SINE COS 8kHz SINE SEQUENCE GENERATOR O 1 OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M CLK SPEECH GND GND X Y LINE CODE FUNCTION GENERATOR ANALOG I/ O ACH1 ACH0 DAC0 VARIABLE DC + DAC1 UTILITIES COMPARATOR REF IN RECTIFIER DIODE & RC LPF RC LPF OUT FGEN TRIG 5V TTL SCOPE 10VDC 7Vrms max CH 0 CH 1 DUAL ANALOG SWITCH TUNEABLE LPF S/ H S&H IN S&H OUT f C x100 IN 1 CONTROL 1 CONTROL 2 f C GAIN IN 2 OUT IN OUT

212

213

214 V V f f

215

216

217 MASTER SIGNALS SINE COS 8kHz SINE SEQUENCE GENERATOR O 1 OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M CLK SPEECH GND GND X Y LINE CODE FUNCTION GENERATOR ANALOG I/ O ACH1 ACH0 VARIABLE DC + DAC1 DAC0 FGEN TRIG 5V TTL SCOPE 10VDC 7Vrms max CH 0 CH 1

218

219

220

221

222 MASTER SIGNALS SEQUENCE GENERATOR CHANNEL MODULE FUNCTION GENERATOR FGEN O LINE CODE TRIG 5V TTL SINE COS 8kHz SINE 1 OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M CLK SPEECH GND GND X Y NOISE BASEBAND LPF SIGNAL CHANNEL BPF ADDER CHANNEL OUT ANALOG I/ O ACH1 ACH0 VARIABLE DC + DAC1 DAC0 SCOPE 10VDC 7Vrms max CH 0 CH 1

223

224

225 MASTER SIGNALS SEQUENCE GENERATOR CHANNEL MODULE FUNCTION GENERATOR FGEN SINE COS 8kHz SINE O 1 OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M CLK SPEECH GND GND X Y LINE CODE NOISE BASEBAND LPF SIGNAL CHANNEL BPF ADDER CHANNEL OUT ANALOG I/ O ACH1 ACH0 VARIABLE DC + DAC1 DAC0 TRIG 5V TTL SCOPE 10VDC 7Vrms max CH 0 CH 1 TUNEABLE LPF UTILITIES COMPARATOR REF f C x10 0 IN OUT RECTIFIER f C DIODE & RC LPF GAIN RC LPF IN OUT

226

227 MASTER SIGNALS SINE COS 8kHz SINE SEQUENCE GENERATOR O 1 OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M CLK SPEECH GND GND X Y LINE CODE CHANNEL MODULE NOISE BASEBAND LPF SIGNAL CHANNEL BPF ADDER CHANNEL OUT FUNCTION GENERATOR ANALOG I/ O ACH1 ACH0 VARIABLE DC + DAC1 DAC0 FGEN TRIG 5V TTL SCOPE 10VDC 7Vrms max CH 0 CH 1 TUNEABLE LPF UTILITIES COMPARATOR REF f C x100 IN OUT RECTIFIER f C DIODE & RC LPF GAIN RC LPF IN OUT

228

229

230 µs kHz (1:1) 0.4 1ms kHz 3kHz 5kHz 7kHz and so on

231 1 250µs ms 1kHz (1:3) 0 1kHz 2k 3kHz 5kHz 6k 7kHz 9kHz and so on

232

233 MASTER SIGNALS SINE COS 8kHz SINE SEQUENCE GENERATOR O 1 OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M CLK SPEECH GND GND X Y LINE CODE FGEN TRIG 5V TTL SCOPE 10VDC 7Vrms max CH 0 CH 1

234

235

236

237 MASTER SIGNALS SINE COS 8kHz SINE SEQUENCE GENERATOR O 1 OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M CLK SPEECH GND GND X Y LINE CODE FGEN TRIG 5V TTL SCOPE 10VDC 7Vrms max CH 0 CH 1

238

239

240

241

242

243

244

245 FUNCTION GENERATOR SEQUENCE GENERATOR O LINE CODE TUNEABLE LPF ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + 1 OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M CLK SPEECH GND X Y f C GAIN f C x100 SCOPE 10VDC 7Vrms max CH 0 CH 1 GND IN OUT

246

247

248 FUNCTION GENERATOR SEQUENCE GENERATOR O LINE CODE TUNEABLE LPF ANALOG I/ O ACH1 DAC1 ACH0 DAC0 VARIABLE DC + 1 OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M CLK SPEECH GND X Y f C GAIN f C x100 SCOPE 10VDC 7Vrms max CH 0 CH 1 GND IN OUT

249

250

251 Name: Class: 15 — Line coding and bit-clock regeneration

252 Experiment 15 Line coding and bit-clock regeneration Preliminary discussion Line coding As you know, logic-0 and logic-1 in digital systems are represented by assigned voltages. For example, the TTL logic-0 is represented by 0V and the TTL logic-1 is represented by 5V (or by acceptable voltages relatively close to 0V and 5V). As you also know, the logic levels for other logic families like CMOS, ECL, etc are not necessarily 0V and 5V. This tells us that logic levels can be represented by any pair of voltages we like. That said, the choice of which voltages to use is not as arbitrary as that may seem. It s usually an engineering decision made to confer an advantage. Importantly, this is also true for the choice of voltages used when sending digital signals over transmission lines like telephone lines. Standard TTL and CMOS voltages are less than ideal for this purpose. Moreover, even the basic premise of holding the voltage at a particular value for the entire duration of the logic state s value can be disadvantageous. For these reasons, digital signals within systems are often conditioned for transmission line communications and this is called line coding. There are quite a few line codes. Four of them are: Non-return to zero level (bipolar) (NRZ-L) As you can see from Figure 1 on the next page, this code is a simple scale and level shift of the original digital signal. Bi-phase level (BiΦ-L also known as Manchester code) Figure 1 shows that this code changes state from +V to V in the middle of the bit period for all logic-1s and changes from V to +V in the middle of the bit period for all logic-0s. For consecutive bits with the same logic level, the voltage must invert after half a bit length in order to satisfy this rule for the next bit. Return to zero alternate mark inversion (RZ-AMI) Figure 1 shows that this code uses 0V to represent logic-0 and a half-bit pulse to represent logic-1. Importantly, the polarity of the pulses alternates for every successive logic-1 (even if they re not consecutive bits). Non-return to zero mark (bipolar) (NRZ-M) Figure 1 shows that this code changes state for each new logic-1 and doesn t change state for any logic-0s Emona Instruments Experiment 15 Line coding & bit clock regeneration

253 V TTL 0V NRZ-L 0V Bio-L 0V RZ-AMI 0V NRZ-M 0V Figure 1 Table 1 below compares the minimum bandwidth requirements for propagating these signals along transmission lines. It also shows the line code s usefulness for bit-clock regeneration. Line code NRZ-L Table 1 Minimum bandwidth f b 2 Bit-clock regeneration Poor BiΦ-L f b Very good RZ-AMI NRZ-M f b 2 f b 2 Good Poor Experiment 15 Line coding & bit clock regeneration Emona Instruments 15-3

254 As you can see, RZ-AMI offers the best compromise of the four between bandwidth and bitclock regeneration (as well as other line code characteristics not mentioned here) and so it is widely used. Bit-clock regeneration In digital communications, once the transmitted signal has been demodulated by the receiver and the digital data signal cleaned up, the data bits are read. Whatever the circuit or device that does the reading, it must have a bit-clock that is synchronised to the bit-clock of the original digital data. If not, some bits are read more than once and/or other bits are not read at all. Both result in data errors. When implementing other DATEx digital experiments, bit-clock synchronisation is achieved by simply stealing the bit-clock using a patch lead. This is obviously not possible in practice for wireless communications and is impractical for transmission line communications because an additional line is needed. As such, a method of remotely synchronising the two bit-clocks is necessary. This is the aim of bit-clock regeneration (BCR). There are many ways of implementing bit-clock regeneration. To understand open-loop methods of BCR, you have to understand that the spectral composition of the digital data signal consists of a fundamental and harmonics that are sub-multiples and multiples of the original data s bit-clock (this issue is examined in Experiment 14). Usefully, the spectral composition of line codes such as Bi-phase level (BiΦ-L or Manchester code) consist of a significant harmonic at the original bit-clock. In which case, this harmonic can be recovered using an appropriately selective band-pass filter. Others line codes (like the other three mentioned on page 15-2) don t have a significant harmonic at the bit-clock frequency. However, their spectral composition is such that, if the digital data signal is mathematically squared, a significant sinewave at the original digital data signal s bit-clock is generated. Again, this signal can be recovered using an appropriately selective band-pass filter. Once the sinewave at the bit-clock frequency has been filtered, it is sent to a comparator to convert it into a digital signal and is then ready to be used as the local bit-clock (notwithstanding other bit-clock regeneration issues such as jitter). The experiment For this experiment you ll examine the four DATEx line code equivalents of a standard TTL data signal in the time domain and compare them to their theoretically predicted waveshape. Next you ll examine the signals in the frequency domain to establish that one of them is different to the other three in terms of its spectral composition. Finally, you ll square the line codes to observe the effect on the component in them at the bit-clock frequency. It should take you about 50 minutes to complete this experiment Emona Instruments Experiment 15 Line coding & bit clock regeneration

255 Pre-requisites: Experiments 1, 2 & 3 (Vol. 1): Intros to the NI ELVIS II, the Emona DATEx and SFP control Experiment 14 (Vol. 2): PN sequence spectrum and noise generation (desirable) Equipment Personal computer with appropriate software installed NI ELVIS II plus USB cable and power pack Emona DATEx experimental add-in module Three BNC to 2mm banana-plug leads Assorted 2mm banana-plug patch leads Procedure Part A Observations of line codes in the time domain The next part of this experiment gets you observe the four Emona DATEx line code outputs in the time domain. 1. Ensure that the NI ELVIS II power switch at the back of the unit is off. 2. Carefully plug the Emona DATEx experimental add-in module into the NI ELVIS II. 3. Set the Control Mode switch on the DATEx module (top right corner) to PC Control. 4. Connect the NI ELVIS II to the PC using the USB cable. Note: This may already have been done for you. 5. Turn on the NI ELVIS II power switch at the rear of the unit then turn on its Prototyping Board Power switch at the top right corner near the power indicator. 6. Turn on the PC and let it boot-up. 7. Launch the NI ELVISmx software. 8. Launch the DATEx soft front-panel (SFP) and check that you have soft control over the DATEx board. 9. Locate the Sequence Generator module on the DATEx SFP and set its soft DIP-switches to 00. Note: This selects NRZ-L as the line code for the Sequence Generator module s LINE CODE output. Experiment 15 Line coding & bit clock regeneration Emona Instruments 15-5

256 10. Connect the set-up shown in Figure 2 below. Note: Insert the black plugs of the oscilloscope leads into a ground (GND) socket. MASTER SIGNALS SINE COS 8kHz SINE SEQUENCE GENERATOR O 1 OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M CLK SPEECH GND GND X Y LINE CODE FGEN TRIG 5V TTL SCOPE 10VDC 7Vrms max CH 0 CH 1 Figure 2 This set-up can be represented by the block diagram in Figure 3 below. The Master Signals module s output is used to provide the Sequence Generator module s bit-clock. The Sequence Generator module s X output is a continuous 31-bit sequential binary number. The Sequence Generator module s LINE CODE output is a copy of its X output using the line code scheme set by the DIP-switches. The module s SYNC output is a pulse that corresponds with the sequences first output bit on every repetition and is used to trigger the scope. Master Signals Clock CLK X SYNC Sequence Generator LINE CODE X sequence To CH 0 Line code To CH 1 SYNC To TRIG Figure Emona Instruments Experiment 15 Line coding & bit clock regeneration

257 11. Launch and run the NI ELVIS II Oscilloscope VI. 12. Adjust the scope to view the Sequence Generator module s X output as a stable display. Essential scope settings include: Timebase to 1ms/div Trigger Type to Digital Note: You ll now be viewing a portion of the X output s 31-bit sequence. 13. Activate the scope s Channel 1 input (by checking the Channel 1 Enabled box) to view both the Sequence Generator module s X and LINE CODE outputs. Note: The signals will be overlayed. 14. Set the scope s Channel 1 Vertical Position control to -3V to separate the signals and make them easier to compare. Note 1: Once done, the Channel 1 0V reference no-longer corresponds with the middle horizontal line on the graticule. However, the reference s new position is shown using a thin blue dashed line. Note 2: Notice that the Channel 1 0V reference runs through the middle of the line code signal. This means that one of signal s voltages is positive and the other negative. 15. Draw the two waveforms to scale and time-coincident with each other in the space provided on the next page. Note: Leave room for three more signals. 16. Select the BiΦ-L line code by setting the Sequence Generator module s soft DIPswitches to Draw the line code signal time-coincident with the other two. 18. Select the RZ-AMI line code by setting the Sequence Generator module s soft DIPswitches to 10 and draw the signal time-coincident with the others. 19. Select the NRZ-M line code by setting the Sequence Generator module s soft DIPswitches to 11 and draw the signal time-coincident with the others. Ask the instructor to check your work before continuing. Experiment 15 Line coding & bit clock regeneration Emona Instruments 15-7

258 15-8 Emona Instruments Experiment 15 Line coding & bit clock regeneration

259 Ask the instructor to check your work before continuing. 20. Compare each of the line code signals with the rules underpinning them summarised in the preliminary discussion. Note: If any the signals appear to change when they shouldn t or don t change when they should, check your drawing. If your drawing is correct, call the instructor for assistance. Question 1 Which of the four line codes is bi-polar? Question 2 Which of the four line codes represents the logic-0 in the data using 0V? Question 3 Use the rule for RZ-AMI to determine the number of logic-1s in the portion of the X output s data sequence being displayed. Ask the instructor to check your work before continuing. Experiment 15 Line coding & bit clock regeneration Emona Instruments 15-9

260 Part B Observations of line codes in the frequency domain The next part of this experiment gets you observe the four Emona DATEx line code outputs in the frequency domain. 21. Select the NRZ-L line code by returning the Sequence Generator module s soft DIPswitches to Close the scope s VI. 23. Launch and run the NI ELVIS II Dynamic Signal Analyzer VI. Note: If the Dynamic Signal Analyzer VI has launched successfully, the instrument s window will be visible (see Figure 4). Figure Emona Instruments Experiment 15 Line coding & bit clock regeneration

261 24. Adjust the signal analyzer s controls as follows: Input Settings Source Channel to SCOPE CH 1 Voltage Range to ±10V FFT Settings Frequency Span to 40,000 Resolution to 400 Window to 7 Term B-Harris Averaging Mode to RMS Weighting to Exponential # of Averages to 3 Trigger Settings Type to Digital Frequency Display Units to db Cursors On box unchecked (for now) Mode to RMS Scale to Auto Once adjusted correctly, the signal analyzer s display should look like Figure 5 below. Figure 5 Experiment 15 Line coding & bit clock regeneration Emona Instruments 15-11

262 If you ve not used the signal analyzer before, its display may need a little explaining here. There are actually two displays, a large one on top and a much smaller one underneath. The smaller one is a time domain representation of the input (in other words, the display is a scope). The larger of the two displays is the frequency domain representation of the 31-bit sequence on the Sequence Generator module s LINE CODE output. The pattern of humps (or lobes) and nulls is typical of digital data signals (for reasons explained in Experiment 14). 25. Compare the spectral composition of the four line codes. Note: You should observe that, while all four codes exhibit the pattern mentioned above, their spectral composition is different. Recall that this is one of the reasons for choosing to use one code over another. One of the disadvantages of BiΦ-L (Manchester code) is that it requires twice the bandwidth of the other three codes to propagate the signal along a transmission line. While this limitation cannot be demonstrated using the DATEx directly, we can examine the spectrum of the four signals more closely to see that BiΦ-L is different to the other three in important ways. 26. Adjust the Sequence Generator module to output the NRZ-L line code. 27. Count the number of lobes in the signal s spectrum (for a span of 40kHz). Record this number in Table 2 below. 28. Repeat Steps 26 and 27 for the other three codes. Line code Table 2 Lobes (in 40kHz span) NRZ-L BiΦ-L RZ-AMI NRZ-M Ask the instructor to check your work before continuing Emona Instruments Experiment 15 Line coding & bit clock regeneration

263 To compare BiΦ-L to the other codes in another way, we ll use the signal analyzer s cursors to examine the null frequencies. 29. Activate the signal analyzer s cursors by checking (that is, ticking) Cursors On box. Note 1: When you do, green horizontal and vertical lines should appear on the signal analyzer s frequency domain display. Note 2: If you have used the signal analyzer s cursors before, jump to Step 34 on the next page. The NI ELVIS II Dynamic Signal Analyzer has two cursors C1 and C2 that default to the left most side of the display when the signal analyzer s VI is launched. They re repositioned by grabbing their vertical lines with the mouse and moving the mouse left or right. 30. Use the mouse to grab and move the vertical line of cursor C1. Note: As you do, notice that cursor C1 moves along the signal analyzer s trace and that the vertical and horizontal lines move so that they always intersect at C Repeat Step 30 for cursor C2. Note: Fine control over the cursors position is obtained by using the cursor s Position control in the Cursor Settings area (below the display). The NI ELVIS II Dynamic Signal Analyzer includes a tool that measures the difference in magnitude and frequency between the two cursors. This information is displayed in green between the upper and lower parts of the display. 32. Move the cursors while watching the measurement readout to observe the effect. 33. Position the cursors so that they re on top of each other and note the measurement. Note: When you do, the measurement of difference in magnitude and frequency should both be zero. Usefully, when one of the cursors is moved to the extreme left of the display, its position on the X-axis is zero. This means that the cursor is sitting on 0Hz. It also means that the measurement readout gives an absolute value of frequency for the other cursor. This makes sense when you think about it because the readout gives the difference in frequency between the two cursors but one of them is zero. Experiment 15 Line coding & bit clock regeneration Emona Instruments 15-13

264 34. Adjust the Sequence Generator module to output the NRZ-L line code. 35. Move C1 to the extreme left of the display. 36. Align C2 with the first null (that is, the deep trough between the first and second lobes in the signal s spectrum). 37. Measure the null s frequency and record this in Table 3 below. 38. Measure and record the frequency of the first null in the spectrum of the other three line codes. Line code Table 3 Frequency of first null NRZ-L BiΦ-L RZ-AMI NRZ-M Question 4 Based on your results in Tables 2 and 3, which of the four codes is the odd one out? Ask the instructor to check your work before continuing Emona Instruments Experiment 15 Line coding & bit clock regeneration

265 Part C Bit-clock regeneration without squaring Recall from the preliminary discussion that, for line codes containing a significant spectral component at the bit-clock frequency, BCR simply involves using a band-pass filter with an appropriate selectivity to pick-out the bit-clock component. Naturally, this is a sinewave but it can be readily turned into a squarewave using a comparator and used as a local bit-clock. Line codes vary in terms of the significance of their bit-clock component. The next part of the experiment demonstrates this. 39. Adjust the Sequence Generator module to output the NRZ-L line code. 40. Set the signal analyzer s Frequency Span to 4,000Hz instead of 40,000Hz. 41. Use the C2 cursor to locate the sinewave in the line code signal s spectrum that is at the bit-clock frequency. Note: The Master Signals module s output is actually 2.083kHz. So, the bit-clock component is the sinewave at or very near this frequency. 42. Determine the component s relative size and record the value in Table 4 below. Note 1: The relative size of the component is determined by following the horizontal dashed line from the cursor s to the Y-axis and reading off its db figure. Note 2: This is the component s size in decibels relative to the largest component in the line code signal. 43. Convert the db figure to a ratio using the equation: A V 1 db = Log ( ) Determine the relative size of the component at the bit-clock frequency in the other three line codes (in both db and as a ratio). Line code NRZ-L Table 4 Bit-clock component (in db) Bit-clock comp. (as a ratio) BiΦ-L RZ-AMI NRZ-M Experiment 15 Line coding & bit clock regeneration Emona Instruments 15-15

266 Question 5 Which of the DATEx line codes has the biggest component at the original bit-clock frequency? Ask the instructor to check your work before continuing Emona Instruments Experiment 15 Line coding & bit clock regeneration

267 Part D Bit-clock regeneration with squaring For line codes without a significant spectral component at the bit-clock frequency, BCR necessarily involves squaring the signal first. This generates a more significant spectral component at the bit-clock frequency that may be significant enough to be readily filtered and cleaned-up with a comparator for use as a local bit-clock. The next part of the experiment demonstrates this. 45. Adjust the Sequence Generator module to output the NRZ-L line code. 46. Locate the Tuneable Low-pass Filter module on the DATEx SFP and set its soft Gain control to about the middle of its travel. 47. Turn the Tuneable Low-pass Filter module s soft Cut-off Frequency Adjust control fully clockwise. 48. Modify the set-up as shown in Figure 6 below. Note: Remember that the dotted lines show leads already in place. MASTER SIGNALS SEQUENCE GENERATOR TUNEABLE LPF MULTIPLIER FGEN O LINE CODE TRIG 5V TTL SINE COS 8kHz SINE 1 OO NRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M CLK SPEECH GND GND X Y IN f C GAIN f C x10 0 OUT X DC Y DC SERIAL kxy SERIAL TO PARALLEL CLK S/ P X1 X2 SCOPE 10VDC 7Vrms max CH 0 CH 1 Figure 6 Experiment 15 Line coding & bit clock regeneration Emona Instruments 15-17

268 The set-up in Figure 6 can be represented by the block diagram in Figure 7 below. The Tuneable Low-pass Filter module is used to model signal-shaping to reduce signal s bandwidth. The Multiplier module is used to multiply the shaped line code signal with itself effectively squaring it. This multiplies every sinewave in the signal with each other producing a multitude of sum and difference frequencies. Some of these sinewaves are the same frequency as the component in the signal at the original data signal s bit-clock frequency and so add to and enlarge it. X sequence To CH 0 X Tuneable Low-pass filter Multiplier module Clock CLK SYNC LC Y X Squared line code To CH 1 SYNC To TRIG Figure Use the C2 cursor to locate the sinewave in the squared line code signal s spectrum that is at the bit-clock frequency. 50. Determine the component s relative size and record the value in Table 4 below. 51. Determine the relative size of the component at the bit-clock frequency in the other three line codes. Line code Table 5 Bit-clock component (in db) NRZ-L BiΦ-L RZ-AMI NRZ-M Emona Instruments Experiment 15 Line coding & bit clock regeneration

269 Question 6 Compare the Figures in Table 5 with those in Table 4. What effect does squaring the line code s signal have on the sinewave in its spectrum at the bit-clock frequency? Question 7 Which of the squared line codes has the biggest component at the original bit-clock frequency? Question 8 What is needed to pick this sinewave out of the signal s spectrum and turn it into a squarewave? Ask the instructor to check your work before finishing. Experiment 15 Line coding & bit clock regeneration Emona Instruments 15-19

270 15-20 Emona Instruments Experiment 15 Line coding & bit clock regeneration

271 Name: Class: 16 — Delta modulation and demodulation

272 Experiment 16 Delta modulation and demodulation Preliminary discussion Despite its cryptic name, delta modulation (or modulation) is a pulse modulation scheme. Other examples of pulse modulation schemes that you may have learnt more about using the Emona DATEx include: pulse amplitude modulation (PAM), pulse code modulation (PCM) and pulse-width modulation (PWM). Delta modulation is like PWM in that it samples the analog input signal and converts it directly into a serial stream of 1s and 0s without the need for a discrete analog-to-digital conversion process. As such, delta modulation is also like PWM in that the digital signal on the delta modulator s digital output is a complex waveform that includes a component at the message frequency. Despite the similarity between delta modulation and PWM, it s actually more useful to describe its operation by comparing it to that of PCM. PCM samples the analog input signal at fixed intervals and the samples are converted to fixed length sequential binary numbers. Importantly, these binary numbers are directly (or, in some cases, mathematically) proportional to the samples size. Delta modulation effectively samples the analog input signal at regular fixed intervals also. However, it then compares the present sample to the previous one and outputs a 1-bit data word to indicate whether the new sample is smaller or larger than the previous one. The block diagram of a basic delta modulation system is shown in Figure 1 below. Input + Limiter Sampler Delta mod. signal out — Clock Integrator Figure Emona Instruments Experiment 16 Delta modulation and demodulation

273 As the delta modulation system in Figure 1 is a feedback loop, a mathematical analysis of its operation is complicated and not attempted here. For the purpose of this exercise, think of its operation in the following way. The Sampler s output (which is also the modulator s output) is a bi-polar pulse train. That is, instead of using 0V and 5V for the two logic states, positive and negative voltages are used (eg ±2.5V). This is done so that the Integrator produces a ramp voltage that changes direction in response to changes in logic state on the Sampler s output. The Integrator s output is subtracted from the message using a Summing circuit to produce an error signal. The polarity of the error signal is a function of the relative absolute voltages of the analog input (the message) and Integrator s output. So, if the Integrator s output is greater than the message, the error signal is one polarity. If the Integrator s output is smaller than the message the error signal is the opposite polarity. This allows the modulator to know which of the two signals is bigger (though this information is captured only at the moment of sampling see below) and this is essential for achieving an Integrator output that approximates the message. Specifically, the Integrator s output hunts the analog input voltage and so its positive or negative going ramp voltages produce a sawtooth waveform that tracks the message signal s shape (and this can be seen in Figure 2 on the next page). The Limiter continuously converts the status of the relative sizes of the sawtooth and message waveforms to a logic state. That is, one logic state indicates when the sawtooth waveform is bigger than the message but reverses the moment that it is smaller. The Sampler samples this information to convert it to clocked data and level translates it to the corresponding positive or negative voltage (mentioned above). Importantly, by definition, sampling is a periodic process and so the Sampler s output only reflects the relative sizes of the sawtooth and message waveforms at the sampling moment. Now let s put this together. At switch-on, the Sampler s output starts at either a positive or negative voltage which commences a ramp on the Integrator s output. Now, suppose that the Integrator s output is smaller than the message (a likely proposition) but travelling in the same direction. This produces an error signal on the Summer s output with a particular polarity that is immediately converted to a particular logic state by the Limiter. This logic state is captured on sampling and a decision is made by the Sampler to maintain its output voltage. In other words, nothing changes. These conditions are maintained for every sample until such time as the absolute ramp voltage exceeds absolute message voltage (either because the ramp catches up with the message or the message reverses direction). Once this happens, the polarity of the error signal reverses which immediately causes the logic state on the Limiter s output to reverse. This new logic state is sampled and captured by the Sampler forcing to reverse its output voltage, in turn causing the Integrator s ramp to reverse direction. These new conditions are now maintained for every sample until such time as the ramp returns to an absolute voltage that is smaller than the absolute message voltage. Experiment 16 Delta modulation and demodulation Emona Instruments 16-3

274 Figure 2 below shows an example of the sawtooth waveform that would be generated on the Integrator s output and the digital signal on the Sampler s output for a sinusoidal message to a delta modulator. (Note: The clock frequency of the Sampler in this example is three times the message frequency.) Figure 2 There is an interesting point to observe about these signals. At first glance, it appears as though the sampling rate is irregular. However, this is not the case. In instances where there are wider than normal gaps between the changes in the ramp s direction, sampling has taken place. But, as the relative relationship between the sawtooth waveform and the message is the same as the previous sample, there is no change of direction in the sawtooth waveform and therefore no change in logic state on the Sampler s output. Finally, Figure 1 shows a discrete amplifier section between the Sampler and the Integrator to control the loop gain. In practice the amplification can be incorporated into the Integrator or Summer circuits Emona Instruments Experiment 16 Delta modulation and demodulation

275 The experiment For this experiment you ll use the Emona DATEx to implement the delta modulation scheme. You ll then experiment with adjusting the integrator s step size to observe the effect on the delta modulator s slope overload and granularity characteristics. Finally, you ll demodulate the delta signal using low-pass filtering and investigate the quality of the recovered message qualitatively and quantitatively using SNDR. It should take you about 50 minutes to complete this experiment. Pre-requisites: Experiments 1, 2 & 3 (Vol. 1): Intros to the NI ELVIS II, the Emona DATEx and SFP control Experiment 13 (Vol. 1): Sampling and reconstruction Experiment 10 (Vol. 2): Pulse code modulation and signal-to-noise distortion ratio Experiment 14 (Vol. 1): PCM encoding (desirable) Experiment 15 (Vol. 1): PCM decoding (desirable) Experiment 6 (Vol. 2): Pulse-width modulation and demodulation (desirable) Equipment Personal computer with appropriate software installed NI ELVIS II plus USB cable and power pack Emona DATEx experimental add-in module Two BNC to 2mm banana-plug leads Assorted 2mm banana-plug patch leads Experiment 16 Delta modulation and demodulation Emona Instruments 16-5

276 Procedure Part A Setting up the delta modulator Part A of this experiment gets you to implement the delta modulator using the Emona DATEx. 1. Ensure that the NI ELVIS II power switch at the back of the unit is off. 2. Carefully plug the Emona DATEx experimental add-in module into the NI ELVIS II. 3. Set the Control Mode switch on the DATEx module (top right corner) to PC Control. 4. Connect the NI ELVIS II to the PC using the USB cable. Note: This may already have been done for you. 5. Turn on the NI ELVIS II power switch at the rear of the unit then turn on its Prototyping Board Power switch at the top right corner near the power indicator. 6. Turn on the PC and let it boot-up. 7. Launch the NI ELVISmx software. 8. Locate the Adder module and set its soft G and g controls to the middle of their travel (which should have the arrowheads pointing to the 12 o clock position). 9. Connect the set-up shown in Figure 3 below. MASTER SIGNALS ADDER UTILITIES COMPARATOR MULTIPLIER REF X DC SINE COS 8kHz SINE A B G g GA+gB GND IN OUT RECTIFIER DIODE & RC LPF RC LPF Y DC kxy SERIAL TO PARALLEL SERIAL CLK S/ P X1 X2 Figure 3 This set-up can be represented by the block diagram in Figure 4 on the next page. The Master Signals module s SINE output models the message. The remaining blocks implement the delta modulator Emona Instruments Experiment 16 Delta modulation and demodulation

….. Expt 4 — 1

5 — Amplitude modulation (AM)………………………………………………………………….. (AM)………………………………………………………………….. Expt 5 — 1 6 — Double Sideband (DSBSC) modulation………………………………………………… modulat ion………………………………………………… Expt 6 — 1 7 — Observations of AM and DSBSC DSBSC signals in the frequency frequency domain domain ….. Expt 7 — 1 8 — AM demodulation …………………………………………………………. …………………………………………………………………………………… ……………………….. Expt 8 — 1 9 — Double Sideband DSBSC demodulation….. demodulation ………. ………. ……….. ………… ……….. ……….. ………… ………… ……….. ….. Expt 9 — 1 10 — Single Sideband (SSB) modulation & demodulation demodulation…… ……….. ………. ………. ………. ………. ….. Expt 10 — 1 11 — Frequency Frequency Modulation (FM) ……….. …………….. ………… ………… ………… ………… ……….. ……….. ………… ………… ………… ……….. ….. Expt 11 — 1 12 — FM demodulation…………………………………………. demodulat ion………………………………………………………………………… ………………………………………. ……….. Expt 12 — 1 13 — Sampling & reconstruction ………… ……………… ………… ………… ………… ………… ……….. ……….. ………… ………… ………… ……….. ….. Expt 13 — 1 14 — PCM encoding ………………………………………………………… ……………………………………………………………………………………….. …………………………….. Expt 14 — 1 15 — PCM decoding ………………………………………………………… ……………………………………………………………………………………….. …………………………….. Expt 15 — 1 16 — Bandwidth limiting and restoring digital signals……….. signals……………. ………. ………. ……….. ……….. ….. Expt 16 — 1 17 — Amplitude Shift Keying (ASK) ………. ……………. ………… ……….. ………. ………. ………. ………. ………. ……….. ………… ……….. ….. Expt 17 — 1 18 — Frequency Shift Keying (FSK)………………………… (FSK) ……………………………………………………….. …………………………………. ….. Expt 18 — 1 19 — Binary Phase Shift Keying (BPSK)……………………………………………………… Expt 19 — 1 20 — Quadrature Phase Shift Keying (QPSK) ………. ……………. ………… ……….. ……….. ………… ………… ……….. ….. Expt 20 — 1 21 — Spread Spectrum — DSSS modulation & demodulation demodulation ………. …………… ………. ……… …. Expt 21 — 1 22 — Undersampling Undersampling in Software Defined Radio…………… Radio……………….. ………. ………. ………. ……….. ……….. ….. Expt 22 — 1

  s   n   o    i    t   a   u   q   e    l   e    d   o   m   o    t   x    E    T    A    D   a   n   o   m    E   e    h    t   g   n    i   s    U      4

  :   e   m   a    N

  :   s   s   a    l    C

Experiment 4 – Using the Emona DATEx to model equations Preliminary discussion This may surprise you, but mathematics is an important part of electronics and this is especially true for communications and telecommunications. As you’ll learn, the output of all communications systems can be described mathematically with an equation. Although the math that you’ll need for this manual is relatively light, there is some. Helpfully, the Emona DATEx can model communications equations to bring them to life.

The experiment This experiment will introduce you to modelling equations by using the Emona DATEx to implement two relatively simple equations. It should take you about 40 minutes to complete this experiment.

Equipment 

Personal computer with appropriate software installed



NI ELVIS II plus USB cable and power pack



Emona DATEx experimental add-in module



Two BNC to 2mm banana-plug leads



Assorted 2mm banana-plug patch leads

4-2

© Emona Instruments

Experiment 4 – Using the DATEx to model equations

Something you need to know for the experiment This box contains the definition for an electrical term used in this experiment. Although you’ve probably seen it before, it’s worth taking a minute to read it to check  your understanding. When two signals are 180° out of phase, they’re out of step by half a cycle. This is shown in Figure 1 below. As you can see, the two signals are always travelling in opposite directions. That is, as one goes up, the other goes down (and vice versa).

Figure 1

Experiment 4 – Using the DATEx to model equations

© Emona Instruments

4-3

Procedure In this part of the experiment, you’re going to use the Adder module to add two electrical signals together. Mathematically, you’ll be implementing the equation:

Adder module output = Signal A + Signal B

1.

Ensure that the NI ELVIS II power switch at the back of the unit is off.

2.

Carefully plug the Emona DATEx experimental add-in module into the NI ELVIS II.

3.

Set the Control Mode  switch on the DATEx module (top right corner) to PC Control .

4.

Connect the NI ELVIS II to the PC using the USB cable. Note: This may already have been done for you.

5.

Turn on the NI ELVIS II power switch at the rear of the unit then turn on its Prototyping Board Power  switch at the top right corner near the power indicator.

6.

Turn on the PC and let it boot-up.

7.

Launch the NI ELVISmx software.

Ask the instructor to check  your work before continuing.

8.

Launch and run the NI ELVIS II Oscilloscope virtual instrument (VI).

9.

Set up the scope per the procedure in Experiment 1 (page 1-12) ensuring that the Trigger Source  control is set to CH 0 .

10.

Launch the DATEx soft front-panel (SFP).

11.

Check you now have soft control over the DATEx by activating the PCM Encoder module’s soft PDM/TDM  control on the DATEx SFP. Note: If you’re set-up is working correctly, the PCM Decoder module’s LED on the DATEx board should turn on and off.

4-4

© Emona Instruments

Experiment 4 – Using the DATEx to model equations

12.

Locate the Adder module on the DATEx SFP and set its soft G  and g  controls to about the middle of their travel.

13.

Connect the set-up shown in Figure 2 below. Note: Although not shown, insert the black plugs of the oscilloscope leads into a ground (GND ) socket.

SCOPE 10VDC 7Vrms ma x

MASTER SIGNALS

CH 0

ADDER

CH 1

100kHz SINE G

100kHz COS A

100kHz DIGITAL 8kHz DIGITAL 2kHz DIGITAL

g

2kHz SINE B

GA+gB

Figure 2

This set-up can be represented by the block diagram in Figure 3 below.

A er module

Master Signals A

Output To CH 1

2kHz B

To CH 0 Figure 3

Experiment 4 – Using the DATEx to model equations

© Emona Instruments

4-5

14.

Adjust the scope’s Timebase  control to view two or so cycles of the Master Signals module’s 2kHz SINE  output.

15.

Measure the amplitude (peak-to-peak) of the Master Signals module’s 2kHz SINE  output. Record your measurement in Table 1 on the next page.

16.

Disconnect the lead to the Adder module’s B  input.

17.

Activate the scope’s Channel 1 input by checking the Channel 1 Enabled  box to observe the Adder module’s output as well as its input.

18.

Adjust the Adder module’s soft G  control until its output voltage is the same size as its input voltage (measured in Step 15). Note 1: This makes the gain for the Adder module’s A  input -1. Note 2: Remember that you can use the keyboard’s TAB  and arrow keys for fine adjustment of the DATEx SFP’s controls.

19.

Reconnect the lead to the Adder module’s B  input.

20.

Disconnect the lead to the Adder module’s A  input.

21.

Adjust the Adder module’s soft g  control until its output voltage is the same size as its input voltage (measured in Step 15). Note: This makes the gain for the Adder module’s B  input -1 and means that the Adder module’s two inputs should have the same gain.

22.

Reconnect the lead to the Adder module’s A  input.

The set-up shown in Figures 3 and 4 is now ready to implement the equation:

Adder module output = Signal A + Signal B

Notice though that the Adder module’s two inputs are the same signal: a 4Vp-p 2kHz sinewave. So, for these inputs the equation becomes:

Adder module output = 4Vp-p (2kHz sine) + 4Vp-p (2kHz sine)

4-6

© Emona Instruments

Experiment 4 – Using the DATEx to model equations

When the equation is solved, we get:

Adder module output = 8Vp-p (2kHz sine)

Let’s see if this is what happens in practice.

23.

Measure and record the amplitude of the Adder module’s output.

Table 1

Input voltage

Output voltage

Question 1 Is the Adder module’s measured output voltage exactly 8Vp-p as theoretically predicted? No.

Question 2 What are two reasons for this? 1) Loading (that is, the Adder’s input is not exactly 4Vp-p) 2) The gains aren’t exactly -1.

Ask the instructor to check  your work before continuing.

Experiment 4 – Using the DATEx to model equations

© Emona Instruments

4-7

In the next part of the experiment, you’re going to add two electrical signals together but one of them will be phase shifted. Mathematically, you’ll be implementing the equation:

Adder module output = Signal A + Signal B (with phase shift)

24.

Locate the Phase Shifter module on the DATEx SFP and set its soft Phase Change  control to the 0°  position.

25.

Set the Phase Shifter module’s soft Phase Adjust  control about the middle of its travel.

26.

Connect the set-up shown in Figure 4 below. Note: Insert the black plugs of the oscilloscope leads into a ground (GND ) socket.

SCOPE 10VDC 7Vrms ma x

CH 0

MASTER SIGNALS

PHASE SHIFTER

CH 1

ADDER

LO

100kHz SINE

PHASE

100kHz COS

0

G

O

A

100kHz DIGITAL 180

8kHz DIGITAL

O

2kHz DIGITAL IN

2kHz SINE

OUT

g B

GA+gB

Figure 4

This set-up can be represented by the block diagram in Figure 5 on the next page.

4-8

© Emona Instruments

Experiment 4 – Using the DATEx to model equations

To CH 1

Phase Shifter 2kHz

O

B Output A To CH 0 Figure 5

The set-up shown in Figures 4 and 5 is now ready to implement the equation:

Adder module output = Signal A + Signal B (with phase shift)

The Adder module’s two inputs are still the same signal: a 4Vp-p 2kHz sinewave. So, with values the equation is:

Adder module output = 4Vp-p (2kHz sine) + 4Vp-p (2kHz sine with phase shift)

As the two signals have the same amplitude and frequency, if the phase shift is exactly 180° then their voltages at any point in the waveform is always exactly opposite. That is, when one sinewave is +1V, the other is -1V. When one is +3.75V, the other is -3.75V and so on. This means that, when the equation above is solved, we get:

Adder module output = 0Vp-p

Let’s see if this is what happens in practice.

Experiment 4 – Using the DATEx to model equations

© Emona Instruments

4-9

27.

Adjust the Phase Shifter module’s soft Phase Adjust  control until its input and output signals look like they’re about 180° out of phase with each other.

28.

Disconnect the scope’s Channel 1 lead from the Phase Shifter module’s output and connect it to the Adder module’s output.

29.

Adjust Channel 1’s Scale  control to resize the signal on the display.

30.

Measure the amplitude of the Adder module’s output. Record your measurement in Table 2 below.

Table 2

Output voltage

Question 3 What are two reasons for the output not being 0V as theoretically predicted? 1) The phase difference between the Adder’s two inputs is not exactly 180°; and 2) The gains aren’t exactly the same.

Ask the instructor to check  your work before continuing.

4-10

© Emona Instruments

Experiment 4 – Using the DATEx to model equations

The following procedure can be used to adjust the Adder and Phase Shifter modules so that the set-up has a null  output. That is, an output that is close to zero volts.

31.

Use the keyboard’s TAB  and arrow keys to vary the Phase Shifter module’s soft Phase Adjust  control left and right a little and observe the effect on the Adder module’s output.

32.

Use the keyboard to make the necessary fine adjustments to the Phase Shifter module’s soft Phase Adjust  control to obtain the smallest output voltage from the Adder module.

Question 5 What can be said about the phase shift between the signals on the Adder module’s two inputs now? The phase shift is much closer to 180° (but it’s probably still not exactly 180°)

33.

Use the keyboard to vary the Adder module’s soft g  control left and right a little and observe the effect on the Adder module’s output.

34.

Use the keyboard to make the necessary fine adjustments to the Adder module’s soft g  control to obtain the smallest output voltage.

Question 6 What can be said about the gain of the Adder module’s two inputs now? They’re much closer to each other (but they’re still probably not exactly the same)

You’ll probably find that you’ll not be able to null the Adder module’s output completely. Unfortunately, real systems are never perfect and so they don’t behave exactly according to theory. As such, it’s important for you to learn to recognise these limitations, understand their origins and quantify them where necessary.

Ask the instructor to check  your work before finishing.

Experiment 4 – Using the DATEx to model equations

© Emona Instruments

4-11

4-12

© Emona Instruments

Experiment 4 – Using the DATEx to model equations

Emona DATEx VOLUME 2 Contents 

Introduction ………………………………………………………………………………………….. i — iv 1 — AM (method 2) and product detection of AM signals……………………….. Expt 1 — 1 2 — Noise in AM communications………………………………………………………………… Expt 2 — 1 3 — PCM and time division multiplexing (TDM) …………………………………………. Expt 3 — 1 4 — An introduction to Armstrong’s modulator ………………………………………… Expt 4 — 1 5 — Phase division modulation and demodulation ………………………………………. Expt 5 — 1 6 — Pulse-width modulation and demodulation………………………………………….. Expt 6 — 1 7 — Message translation and inversion ………………………………………………………. Expt 7 — 1 8 — Carrier acquisition using the phase-locked loop ………………………………… Expt 8 — 1 9 — Signal-to-noise ratio and eye diagrams………………………………………………. Expt 9 — 1 10 — Pulse code modulation and signal-to-noise distortion ratio (SNDR) Expt 10 — 1 11 — ASK demodulation using product detection………………………………………. Expt 11 — 1 12 — FSK generation (switching method) and demodulation……………………. Expt 12 — 1 13 — Principles of Gaussian FSK (GFSK) ……………………………………………………. Expt 13 — 1 14 — PN sequence spectra and noise generation

….Expt 14 — 1 15 — Line coding and bit-clock regeneration …………………………………………….. Expt 15 – 1 16 — Delta modulation and demodulation …………………………………………………… Expt 16 — 1 17 – Delta-sigma modulation and demodulation………………………………………… Expt 17 – 1 18 – FM Generation using the harmonic multiplier method…………………….. Expt 18 — 1

  n   o    i    t   a   r   e   n   e   g   e   s    i   o   n    d   n   a   a   r    t   c   e   p   s   e   c   n   e   u   q   e   s    N    P      4    1   :   e   m   a    N

  :   s   s   a    l    C

Experiment 14 – PN sequence spectra and noise generation Preliminary discussion Pseudo-noise sequences (or just PN sequences) are very useful signals in communications and telecommunications, especially for implementing modulation schemes such as DSSS and CDMA (among others). They can also be used to generate noise for experimental purposes when modelling real world communications systems. But what exactly is a PN sequence?

To understand the answer to this question, you must return to the spectral composition of pulse trains. Recall that a pulse train is made up of a theoretically infinite number of sinewaves – the fundamental and its harmonics. Recall also that the frequency and amplitude of a pulse train’s sinusoidal components affects its frequency and mark-space ratio (or duty cycle). Despite this, the spectral composition of all pulse trains follows the pattern of the (truncated) Sinc Function  shown in Figure 1 below. 1 0.8 0.6 0.4 0.2 0 1

2

3

4

-0.2 -0.4

Figure 1

Figure 2 below illustrates this with an example of a 1kHz squarewave (a pulse train with a mark-space ratio of 1:1 or a duty cycle 50%). This is a spectrum that would be familiar to you.

500µs

1 0.8

1kHz (1:1)

0.6

1ms

0.4 0.2 0

3kHz

7kHz and so on…

1kHz

5kHz

-0.2 -0.4

Figure 2

14-2

© Emona Instruments

Experiment 14 – PN sequence spectra & noise generation

Figure 3 below shows the spectral composition of a 1kHz pulse train pulse having a mark-space ratio of 1:3 (or a duty cycle 25%). Notice that it too follows the pattern of the Sinc Function. 250µs 1 0.8

1kHz (1:3)

0.6

1ms

0.4 0.2 0

5kHz 6k 7 kHz 1kHz 2k 3kHz

9kHz and so on…

-0.2 -0.4

Figure 3

The examples in Figures 2 and 3 are instructive. Together, they show us that some harmonics of the pulse trains have an amplitude of zero (or are “nulled”) and this is true of all pulse trains. Second, a comparison of Figures 2 and 3 shows us that, as the pulse train’s mark-space ratio decreases, the number of significant harmonics that make it up increases. Or, put another way, as the mark-space ratio decreases, the number of harmonics that are present in each of the Sinc Function’s lobes increases. Now, suppose a sequence generator continuously outputs the sequential 4-bit binary number 1000 with each bit being 250µs wide (requiring a bit-clock of 4kHz). In the time domain, the resulting digital data signal is identical to the pulse train in Figure 3. This means that the sequence’s spectral composition must be identical to the spectrum in Figure 3 also. This fact has a couple of important implications. First, we can establish a general rule for determining the nulled harmonics in repeated sequential binary number sequences. They correspond with whole number multiples of the digital signal’s bit-clock (that is, fbit, 2fbit, 3fbit and so on). In the case of our repeated sequential 4-bit binary number 1000 generated using a 4kHz bit-clock, the nulls occur at 4kHz, 8kHz, 12kHz and so on to infinity (theoretically). Second, if the sequence generator’s continuously repeated output is changed to the 5-bit binary number sequence 10000, the mark-space ratio of the resulting digital data signal decreases and so more harmonics are present between the nulls. Importantly though, if a 4kHz bit-clock is used to generate the 5-bit sequence, the nulls occur at the same frequencies as our example in Figure 3. So, with the nulls occurring at the same frequencies but with more harmonics between them, the spectral composition of the 5-bit sequence must be richer than that of its 4-bit counterpart. This gives us a second general rule. The greater the number of bits in a repeated sequence for a given bit-clock, the greater the sequence’s spectral composition (though this doesn’t apply to PN sequences with internally repeated sequences like 101010… and 11001100…).

Experiment 14 – PN sequence spectra & noise generation

© Emona Instruments

14-3

Using the Sinc Function to analyse the spectral composition of several binary number sequences like 1000, 10000, 100000 and so on would quickly show that the number of harmonics in each lobe is the same number as the sequence’s length (though the last one is nulled). Finally, we can now return to the question of what is a pseudo-noise sequence. If the length of certain binary number sequences is long enough, their spectral composition becomes so dense that it can be used to model bandwidth limited white noise. That said, there would still be a repetitive element to the “noise signal” and so they’re called pseudo (or “apparent”) noise sequences.

The experiment For this experiment you’ll use the Emona DATEx to consider a 31-bit and 255-bit binary number sequence in the time domain. You’ll then look at the data signals’ spectra in the frequency domain to confirm their spectral composition. Finally, you’ll use the sequences to generate electrical noise and compare their effectiveness.

It should take you about 50 minutes to complete this experiment.

Pre-requisites: Experiments 1, 2 & 3 (Vol. 1): Intros to the NI ELVIS II, the Emona DATEx and SFP control

Equipment 

Personal computer with appropriate software installed



NI ELVIS II plus USB cable and power pack



Emona DATEx experimental add-in module



Three BNC to 2mm banana-plug leads



Assorted 2mm banana-plug patch leads

14-4

© Emona Instruments

Experiment 14 – PN sequence spectra & noise generation

Procedure Part A – Observations of PN sequences in the time domain The next part of this experiment gets you to set up a 31-bit and a 255-bit binary number sequence and consider them in the time domain as preparation for looking at their spectra.

1.

Ensure that the NI ELVIS II power switch at the back of the unit is off.

2.

Carefully plug the Emona DATEx experimental add-in module into the NI ELVIS II.

3.

Set the Control Mode  switch on the DATEx module (top right corner) to PC Control .

4.

Connect the NI ELVIS II to the PC using the USB cable. Note: This may already have been done for you.

5.

Turn on the NI ELVIS II power switch at the rear of the unit then turn on its Prototyping Board Power  switch at the top right corner near the power indicator.

6.

Turn on the PC and let it boot-up.

7.

Launch the NI ELVISmx software.

8.

Connect the set-up shown in Figure 4 below. Note: Insert the black plugs of the oscilloscope leads into a ground (GND ) socket.

MASTER SIGNALS

SEQUENCE GENERATOR LINE CODE O

FGEN TRIG 5V TTL

1 OONRZ-L SYNC O1 Bi-O 1O RZ-AMI 11 NRZ-M 100kHz SINE

CH 0

X

100kHz COS

SCOPE 10VDC 7Vrms ma x

Y CLK

100kHz DIGITAL

SPEECH

CH 1

8kHz DIGITAL 2kHz DIGITAL GND 2kHz SINE GND

Figure 4

Experiment 14 – PN sequence spectra & noise generation

© Emona Instruments

14-5